Job Description:
- Location: Bangalore/Hyderabad/Pune
- Experience: 3-10yrs
Skills required:
- Sound knowledge of RTL design with Verilog/system Verilog and front-end design tools & flows.
- Good experience in Synthesis & Timing Analysis required.
- Experience in developing Micro architecture from specifications and take it upto RTL coding and synthesis.
- Should have worked on IP and SOC level Synthesis for multiple generations and be familiar with problems associated with different Process technologies.
- Should have experience working on Low power synthesis and understands UPF.
- Experience in implementing ECOs.
- IP development and coding using standard coding guide lines.
- Must have strong knowledge of AMBA AHB/AXI protocol.
- Working knowledge on code coverage, functional coverage, Lint, CDC Formality etc.
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